On April 8th 2025 IBM announced the IBM z17 at the new One Madison Avenue headquarters. The fanfare of that event was followed by an IBM Z Day Special Edition which gave participants a deep look inside the new system hardware, along with the latest software innovations that will pair with it, including real world use cases by clients and partners. Replays are now available, and if you’re reading this post and are particularly interested in hardware the “Innovation up close: A sneak peak INSIDE a next generation mainframe” session will be of particular interest to you, plus it’s a real delight to watch.

But on with the blog post!

Fitting into a 19″ rack space just like its predecessor, the IBM z16, the system already has the ability to fit into a familiar spot in the data center. The z17 features configurations spanning 1 to 4 frames.

Inside the 4-frame version you can have up to give 4 CPC drawers and 12 I/O drawers, and up to two RCAs (Radiator Cooling Assembly).

(Source: IBM z17 Technical Guide)

I was also impressed to learn that memory in a fully loaded system maxes out at 64T, up from 40T in its predecessor, which is quite the jump.

At the heart of the machine is the new IBM Telum II processor.

Telum II wafer, being held by yours truly!

I had the pleasure of attending Hot Chips back in August of 2024 where Chris Berry announced the features of this new processor, which includes:

• A new AI accelerator with 4x the available compute power of the one included with the original IBM Telum processor
• A new built-in low-latency data processing unit (DPU) for accelerated I/O
• 8 high-performance cores running at 5.5GHz
• 40% increase in on-chip cache capacity over Telum

(Source: IBM z17 Technical Guide)

One thing I want to call attention to is the DPU. Taken directly from the IBM z17 Technical Guide, section 3.4.7:

“The IBM z17 Data Processing Unit encompasses a comprehensive refactoring of the I/O subsystem. With the DPU, functionality from I/O Adapters’ ASICs is moved into the Z CP chip.”

That’s pretty cool.

And all that memory and processors are packed into the lovely CPC drawer.

IBM z17 CPC Drawer

For a closer look, you can check out the product page that includes Telum II and the full announcement from IBM back in August of 2024: “New Telum II Processor and IBM Spyre Accelerator: Expanding AI on IBM Z”

Which is the perfect segue into talking about the IBM Spyre Accelerator. In collaboration with the brilliant minds of IBM Research, this new AI accelerator is an application-specific integrated circuit (ASIC) specifically designed for AI workloads that’s the team at Research has dubbed an Artificial Intelligence Unit, or AIU.

It features:

• 32 individual accelerator cores
• 25.6 billion transistors using 14 miles of wire
• 5 nm node process technology

IBM Spyre Accelerator head on, chip exposed

It is mounted on a PCIe card for easy management, and can be clustered together with additional Spyre cards. If you’re like me and curious about how we got there, IBM Research published a blog post about their work back in 2022 that gave a glimpse into their work with the original prototype that ultimately became Spyre in “Meet the IBM Artificial Intelligence Unit”, and in November of 2024 they shared some of what comes next in “Charting a path to a more sustainable AI future”. It’s truly been a fascinating journey to watch, and now we’re here!

The IBM z17 Redbooks are now available. Of particular interest will be the IBM z17 Technical Introduction and IBM z17 (9175) Technical Guide where many of the details for this blog post came from, and I think you’ll find that the clearly marked diagrams throughout are a real treat. And many thanks to Kenny Stine for doing a technical review of this blog post before I let it out the door.